Zhiyi  Yu (
虞志益)

Tenure-track associate professor, SYSU-CMU Joint Institute of Engineering

Professor, School of mobile information engineering, SYSU (joint appointed)

Email: yuzhiyi@mail.sysu.edu.cn or zhiyiyu@andrew.cmu.edu

 

 

I am currently looking for M.S and Ph. D students, research assistant, postdoctor researchers, and assistant researchers with strong background in digital VLSI and/or Computer architecture.

For postdoctor researchers, we offer competitive salary and strong connection with CMU. For Ph.D students, we offer SYSU-CMU double degree program and SYSU single degree program. We also offer SYSU-CMU double degree Master program.

Please contact me if you are interested (yuzhiyi@mail.sysu.edu.cn or zhiyiyu@andrew.cmu.edu)

Short Biography

Zhiyi Yu received the B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China, in 2000 and 2003, respectively, and the Ph.D. degree in electrical and computer engineering from the University of California, Davis in 2007. From 2007 to 2008, he was with IntellaSys Corporation, CA, USA. From 2009 to 2014, he was an Associate Professor with the State Key Lab of ASIC & System, Microelectronics Department, Fudan University, China. Currently, he is a tenure-track associate professor with the SYSU-CMU Joint Institute of Engineering, and the joint appointed full professor with the school of mobile information engineering, SYSU.

His research interests include digital VLSI design and computer architecture, with an emphasis on many-core processors. He has published 1 book and over 80 papers including 3 ISSCC paper and 14 IEEE Transactions/Journal. He has served on the Technical Program Committees of many conferences such as ASSCC, VLSI-SOC, ISLPED, MES, APSIPA, SASIMI, NoCArc, and ASICON.

Books (chapters):

  1. Zhiyi Yu, Bevan Baas, “High Performance and Energy Efficient Many-core DSP Systems”, VDM Verlag Dr. Müller Publisher, 2009
  2. Zhiyi Yu, “Towards High-Performance and Energy-Efficient Multi-core Processors”, Second chapter in “CMOS Processors and Memories”, Springer, 2010

Papers (part):

  1. Jianming Yu, Wei Zhou, Yueming Yang, Xiaodong Zhang, Zhiyi Yu, “Manycore Processors Granularity Evaluation Considering Performance, Yield and Lifetime Reliability”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, in press.
  2. Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng, “Low Power Multicore Processor Design with Reconfigurable Same Instruction Multiple Process”, IEEE Transactions on Circuits and Systems II (TCAS-II), VOL. 61, NO. 6, June 2014.
  3. Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming’e Jing, Xiaoyang Zeng, “A 16-core Processor with Shared-Memory and Message-Passing Communications”, IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 61, No. 4, pp. 1081-1094, April 2014.
  4. Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming'e Jing, Xiaoyang Zeng, Zhiyi Yu, “A 65nm 39GOPS/W 24-Core Processor with 11Tb/s/W Packet Controlled Circuit-Switched Double-Layer Network-on-Chip and Heterogeneous Execution Array”, in IEEE International Solid-State Circuits Conference (ISSCC), February 2013, pp. 56-57.
  5. Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming'e Jing, Xiaoyang Zeng, “An 800MHz 320mW 16-Core Processor With Message-Passing and Shared-Memory Inter-Core Communication Mechanisms”, in IEEE International Solid-State Circuits Conference (ISSCC), February 2012, pp. 64-65.
  6. Zhiyi Yu, Bevan Baas, “A Low-Area Multi-link Interconnect Architecture for GALS Chip Multiprocessor”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18. No. 5, pp.750-762, May 2010.
  7. Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Anh Tran, Zhibin Xiao, Eric Work, Jeremy Webb, Paul Mejia, Bevan Baas, “A 167-processor Computational Platform in 65 nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 44, No. 4, pp. 1130-1144, April 2009.
  8. Zhiyi Yu, Bevan Baas, “High Performance, Energy Efficiency, and Scalability with GALS Chip Multiprocessors”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 17, Issue 1, pp. 66-79, Jan. 2009.
  9. Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas, “A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling”, in IEEE Symposium on VLSI Circuits, June 2008, pp. 22-23.
  10. Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas, “AsAP: An Asynchronous Array of Simple Processors”, IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 3, pp. 695-705, March 2008.
  11. Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas, “A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15, No. 10, pp. 1125-1134, October 2007.
  12. Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung, “AsAP: A Fine-grained Multi-core Platform for DSP Applications”, IEEE Micro, Vol. 27, No. 2, pp:34-45, March-April 2007.
  13. Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan Baas, “An Asynchronous Array of Simple Processors for DSP Applications”, in IEEE International Solid-State Circuits Conference (ISSCC), February 2006, pp:428-429.