JIE Seminar: Nanometer IC Design, Manufacturing and Applications: Challenges, Opportunities, and Outlooks

Updated : January 19, 2016
Press release by Yingneng Gu


Jan. 22(Friday), 2016




Lecture Hall 102, JIE Building


Prof. David Z. Pan, The University of Texas at Austin


Dr. Kai Wang from JIE iSense Laboratory



Nanometer IC Design, Manufacturing and Applications: Challenges, Opportunities, and Outlooks


Integrated circuit (IC) is one of the most important inventions in the 20th Century, widely used in all modern electronics. Thanks to the famous Moore’s Law (2015 marks its 50th anniversary), an unbelievable number of transistors can be packed in a small area (e.g., over 10 billion transistor within 1cm2). As the feature size enters the era of extreme scaling (14nm, 11nm, and beyond), IC design and manufacturing challenges are exacerbated, due to the adoption of multiple patterning and other emerging lithography technologies. Meanwhile, new ways of scaling such as 3D-IC have gained tremendous interest and initial industry adoption, and new devices/materials such as nanophotonics are making their headways to on-chip integration. Furthermore, IC design and CAD methodologies are being pushed to new frontiers, e.g., into bio-chips, healthcare, and Internet-of-Things. This talk will discuss some key technology trends and challenges in nanometer IC design and manufacturing, and discuss some opportunities and outlooks.


David Z. Pan received his BS degree from Peking University, and MS/PhD degrees from UCLA. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is currently the Engineering Foundation Professor at the Department of Electrical and Computer Engineering, The University of Texas at Austin. He has published over 230 refereed journal and conference papers. He has served in many journal editorial boards (TCAD, TVLSI, TCAD-I, TCAS-II, TODAES, SCIS, JCST, etc.) and conference organizing/program committees (DAC, ICCAD, DATE, ASPDAC, ISLPED, ISPD, etc.). He is a working group member of the International Technology Roadmap for Semiconductor (ITRS). He has received a number of awards, including the SRC 2013 Technical Excellence Award, DAC Top 10 Author Award in Fifth Decade (2013), DAC Prolific Author Award (2013), ASP-DAC Frequently Cited Author Award (2015), 12 Best Paper Awards (ISPD 2014, ICCAD 2013, ASPDAC 2012, ISPD 2011, IBM Research 2010 Pat Goldberg Memorial Best Paper Award in CS/EE/Math, ASPDAC 2010, DATE 2009, ICICDT 2009, SRC Techcon in 1998, 2007, 2012 and 2015), Communications of the ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), ISPD Routing Contest Awards (2007), eASIC Placement Contest Grand Prize (2009), ICCAD’12 and ICCAD’13 CAD Contest Awards, among others. He is an IEEE Fellow.